1. Field of the Invention
The present invention relates generally to analog to digital convertors (ADCs) and more particularly to fully differential flash ADCs utilizing comparator arrays.
2. Description of the Relevant Art
Standard flash ADCs compare an analog input voltage with reference voltages derived from a resistor string. The architecture is inherently unsymmetrical with respect to the inputs of the required comparator array and, together with the high and nonlinear input capacitance, causes the performance degradation of conventional flash ADCs at high analog frequencies.
A fully differential flash ADC is described in a paper by Petschacher et al. entitled A 10-b 75-MSPS Subranging A/D Converter with Integrated Sample and Hold, IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 25, NO. 6, DECEMBER 1990, pp. 1339-1346.
FIG. 3 depicts the circuit described in the paper. The circuit includes a "differential reference ladder" (DRL) comprising a common emitter differential amplifier 30 with two identical resistor strings 32R and 32L, each including a load resistor and bit resistors, substituting for single collector-coupled load resistors. The differential amplifier comprises first and second npn transistors Q3' and Q4' having their bases coupled to receive a differential input signal and their emitters respectively coupled to emitter resistors 38 and 40, each having resistance RE and for providing emitter degeneration and establishing the overall ADC gain. As is well-known, the common-emitter coupled transistors in Q3' and Q4' and 36 have an amplifier gain of -RC/RE where RC is the sum of the resistances in each load resistor string.
Transistors Q1' and Q2' have their bases coupled to a reference voltage and their emitters respectively coupled to the resistor strings 32L and 32R to facilitate VBE compensation of the transistors Q3' and Q4' in the differential amplifier 30.
While the above-described circuit has many desirable characteristics, it also has significant problems. In particular, the requirement of the emitter resistor to provide emitter degeneration increases the size and complexity of the circuit in an integrated circuit because resistors take up space. In practice, if the DRL consists of 2N resistors then the emitter resistors, RE, require another 2N resistors for a total of 4N resistors.
Additionally, the common emitter differential input stage limits the dynamic range and bandwidth of the input signal, the linearity of the output signal, and the minimum power supply voltage level. The requirement of extra transistors to facilitate VBE compensation further complicates the circuit.